1. Field of the Invention
The present invention relates to semiconductor structures and, more particularly, to a semiconductor structure that reduces the effects of gate cross diffusion and a method of forming the structure.
2. Description of the Related Art
A complimentary metal oxide semiconductor (CMOS) device is a well-known semiconductor device that includes both n-channel (NMOS) and p-channel (PMOS) transistors. Each transistor has spaced-apart source and drain regions, which are separated by a channel, and a gate that lies over and insulated from the channel.
FIGS. 1A-1F show views that illustrates a prior-art semiconductor structure 100. FIG. 1A shows a plan view, while FIG. 1B shows a cross-sectional view taken along line 1B-1B of FIG. 1A, FIG. 1C shows a cross-sectional view taken along line 1C-1C of FIG. 1A, FIG. 1D shows a cross-sectional view taken along line 1D-1D of FIG. 1A, FIG. 1E shows a cross-sectional view taken along line 1E-1E of FIG. 1A, and FIG. 1F shows a cross-sectional view taken along line 1F-1F of FIG. 1A.
As shown in FIGS. 1A-1F, semiconductor structure 100 includes a semiconductor body 110. Semiconductor body 110, in turn, includes a p-type single-crystal-silicon substrate region 112, and a trench isolation structure 114 that touches substrate region 112. Semiconductor body 110 also includes a p-type well 116 and an n-type well 118 that touch substrate region 112 and trench isolation structure 114.
In addition, semiconductor body 110 includes an n-type source 120 and an n-type drain 122 that each touch p-type well 116, and a p-type source 124 and a p-type drain 126 that each touch n-type well 118. Source 120 and drain 122 each include a lightly-doped (n−) region, and a heavily-doped (n+) region. Similarly, source 124 and drain 126 each include a lightly-doped (p−) region, and a heavily-doped (p+) region. Further, source 120 and drain 122 touch, and are separated, by a channel portion 130 of p-well 116, while source 124 and drain 126 touch, and are separated by, a channel portion 132 of n-well 118.
As additionally shown in FIGS. 1A-1F, semiconductor structure 100 also includes a gate insulation region 134 that touches and lies over channel portion 130, and a gate insulation region 136 that touches and lies over channel portion 132. semiconductor structure 100 further includes a gate 140 that touches trench isolation structure 114, gate insulation region 134, and gate insulation region 136. Further, gate 140 lies over channel portion 130 and channel portion 132.
Gate 140, which can be implemented with polycrystalline silicon, includes an n-type gate region 146 that lies over channel portion 130, and a p-type gate region 148 that lies over channel portion 132. N-type gate region 146, which is heavily doped (n+), touches p-type gate region 148, which is also heavily doped (p+).
Further, semiconductor structure 100 includes a non-conductive side wall spacer 150 that touches and laterally surrounds gate 140. In addition, semiconductor structure 100 includes a conductive structure 152 that touches and overlies gate 140. Conductive structure 152 can be implemented with, for example, silicide. (Although not shown, a silicide structure can also lie over each of the sources and drains.)
In operation, p-type well 116, n-type source 120, n-type drain 122, channel portion 130, gate insulation region 134, and gate 140 form an NMOS transistor 160, while n-type well 118, p-type source 124, p-type drain region 126, channel portion 132, gate insulation region 136, and gate 140 form a PMOS transistor 162.
The threshold voltage of a transistor is the gate voltage required to form an inversion layer at the top surface of the channel portion that is sufficient to allow a current to flow from the source region to the drain region. In the case of an NMOS transistor, n-type dopant atoms form the inversion layer, while p-type dopant atoms form the inversion layer in the case of a PMOS transistor.
When a positive drain-to-source voltage VDS is present, and the gate-to-source voltage VGS is more positive than the threshold voltage, NMOS transistor 160 turns on and electrons flow from source region 120 to drain region 122. When the gate-to-source voltage VGS is more negative than the threshold voltage, NMOS transistor 160 turns off and no electrons (other than a very small leakage current) flow from source region 120 to drain region 122.
Similarly, when a negative drain-to-source voltage VDS is present, and the gate-to-source voltage VGS is more negative than the threshold voltage, PMOS transistor 162 turns on and holes flow from source region 124 to drain region 126. When the gate-to-source voltage VGS is more positive than the threshold voltage, PMOS transistor 162 turns off and no holes (other than a very small leakage current) flow from source region 124 to drain region 126.
In order to place more and more transistors on a single die, the physical sizes of the NMOS and PMOS transistors are being continually scaled down. The performances of the NMOS and PMOS transistors have steadily improved as the physical sizes of the transistors have been scaled down.
However, problems arise as the physical sizes of the transistors are scaled down. One problem that arises as a result of reducing the physical sizes of the transistors is known as gate cross diffusion. In gate cross diffusion, the dopant atoms in the gate region of one transistor diffuse over and change the dopant concentration of the dopant atoms in an adjacent gate region.
For example, a number of the dopant atoms in n-type gate region 146 can diffuse over to p-type gate region 148, and thereby change the dopant concentrations of the n-type dopant atoms in gate region 146 and the p-type dopant atoms in gate region 148. This change in the dopant concentrations of the gate regions 146 and 148 can change the threshold voltages of NMOS transistor 160 and PMOS transistor 162 which, in turn, changes the gate voltages required to turn on NMOS transistor 160 and PMOS transistor 162.
One approach to reducing the effect of gate cross diffusion is to reduce the concentration of dopant atoms in the gate regions 146 and 148. With lower dopant concentrations, fewer dopant atoms are available to diffuse over into an adjacent gate region. However, the polycrystalline silicon structure 142 of gate 140 is typically doped at the same time that the source and drain regions are formed. As a result, this approach also reduces the dopant concentrations of the source and drain regions. Reducing the dopant concentrations of the source and drain regions increases the source-to-drain series resistance and, therefore, is not a preferred approach.
Another approach to reducing the effect of gate cross diffusion is to first selectively implant n-type dopant atoms into one region of a conventionally-deposited layer of gate polycrystalline silicon to form an initial n-type gate region. Following this, p-type dopant atoms are selectively implanted into one region of the gate polycrystalline layer to form an initial p-type gate region that touches the initial n-type gate region. After this, the gate polycrystalline silicon layer is etched to form a polycrystalline silicon structure, such as the polycrystalline silicon structure 142 of gate 140.
The n-type gate region and the p-type gate region are then further doped when the source and drain regions are forms. Doping the gate polycrystalline silicon layer before the gate polycrystalline silicon layer has been etched to form a polycrystalline silicon structure allows the dopant concentrations within the n-type and p-type gate regions to be adjusted to account for the effect of gate cross diffusion.